1. Field of Invention
This invention relates in general to a structure and manufacturing method for dynamic random-access-memory (DRAM) capacitors, and more particularly to the structure and manufacturing method for a stacked type capacitor as well as an improved version using a parallel combination of stacked and trench type capacitors.
2. Description of Related Art
DRAM is a kind of volatile memory whose digital signals are stored according to the charging state of the respective capacitors in each of the memory cells. FIG. 1 shows a conventional circuit diagram of a DRAM cell, which comprises a metal-oxide-semiconductor (MOS) transistor 11 with its gate connected to a word line (WL). One source/drain region is connected to a bit line (BL), while the other source/drain region is connected to ground via a capacitor 12. The capacitor 12 can be regarded as the heart for the storage of digital signals in a DRAM cell. When the charges stored in the capacitor 12 are large, the storage capacity for digital signals is increased. Furthermore, the signal read out from the memory by amplification circuits during a read operation will be less affected by noise. For example, soft errors generated by a-particles will be greatly reduced.
There are several methods to increase the charge storage capacity of the capacitor 12. For example, by increasing the surface area of the capacitor 12, the quantity of charges capable of being stored in the capacitor can be increased. The conventional stacked type capacitor (as shown in FIG. 2K) is one such structure for increasing the surface area of the capacitor in a DRAM memory cell.
FIGS. 2A through 2K are a series of cross-sectional views showing the manufacturing steps of a stacked type DRAM capacitor according to a Taiwan Patent No. 262587. First, referring to FIG. 2A, a semiconductor substrate 20 having a MOS transistor 22, a field oxide layer 26 and a conducting layer 27 already formed above is provided. The MOS transistor 22 includes a gate 23, source/drain regions 24 and spacers 25. Using a chemical vapor deposition (CVD) method, a first insulating layer 28 with a thickness of about 1000 .ANG. to 3000 .ANG. is then deposited covering the aforementioned layers. Thereafter, referring to FIG. 2B, the first insulating layer 28, one of the source/drain regions 24 and the semiconductor substrate 20 are sequentially etched to form a trench 29.
Referring next to FIG. 2C, a first conducting layer 210 is then formed over the first insulating layer 28 and the surfaces of the trench 29. For example, the conducting layer can be an impurity doped polysilicon layer having a thickness of about 500 .ANG. to 1500 .ANG.. An annealing operation is next performed so that heat is supplied to the doped ions causing diffusion and hence forming an expanded region as shown by the dash line of FIG. 2C.
Referring next to FIG. 2D, a second insulating layer 211 is formed above the first conducting layer 210, for example, an oxide layer deposited to a thickness of about 4000 .ANG. to 6000 .ANG.. Subsequently, a first screen layer 212 is formed above the second insulating layer 211, for example, a silicon nitride layer deposited to a thickness of about 500 .ANG. to 2000 .ANG.. Thereafter, using photolithographic and etching processes, a pattern is defined on the second insulating layer 211 and the first screen layer 212 to mark out the boundary of the capacitor structure. This is followed by etching, for example, using a plasma etching method, to form sidewalls 213 on the periphery of the second insulating layer 211 and the first screen layer 212.
Referring next to FIG. 2E, in the subsequent step the sidewalls 213 of the second insulating layer 211 is isotropically etched, for example, using a buffered oxide etchant (BOE) having a concentration ratio of 6:1 of ammonium fluoride mixed with hydrofluoric acid.
Referring next to FIG. 2F, a second conducting layer 214 is formed above the exposed surfaces of the first conducting layer 210, the second insulating layer 211 and the first screen layer 212. For example, the second conducting layer 214 can be an impurity doped polysilicon layer having a thickness of about 1000 .ANG. to 3000 .ANG..
Referring next to FIG. 2G, in a subsequent step the second conducting layer 214 is etched back anisotropically, for example, using a plasma etching method, to form conducting spacers 215. The conducting spacers 215 are electrically connected with the first conducting layer 210 for expanding the overall surface area of the conducting layer.
Referring next to FIG. 2H, the residual second insulating layer 211 and first screen layer 212 are removed leaving behind the first conducting layer 210 together with the conducting spacers 215 which become a lower electrode layer 216 of the capacitor structure. The lower electrode 216 can be created, for example, by isotropically etching away the first screen layer 212 and the second insulating layer 211 in sequence using phosphoric acid (H3PO4) and a buffered oxide etchant having a concentration ratio of 6:1.
Referring next to FIG. 21, a dielectric layer 217 is then formed on the surface of the lower electrode layer 216. The dielectric layer 217, for example, can be a silicon oxide/silicon nitride/silicon oxide (ONO) composite layer formed by first forming a silicon oxide layer through a heat growing method, then forming a silicon nitride layer above, and lastly performing a thermal oxidation operation to form a silicon oxide layer above the silicon nitride layer. Subsequently, a third conducting layer 218a is formed above the dielectric layer 217, for example, by depositing a polysilicon layer containing impurities.
Referring next to FIG. 2J, the third conducting layer 218a is etched to form the boundary of the capacitor structure, for example, by photolithographic and plasma etching processes, thereby forming the upper electrode 218.
Lastly, referring to FIG. 2K, a metalization procedure is performed by first depositing a boro-phosphosilicate glass (BPSG) layer 219 on top of the upper electrode 218, then etching the layer to form contact windows, and finally sputtering a metal layer 220 on top of the boro-phosphosilicate glass layer 219.
Although the above stacked type DRAM capacitor structure is capable of increasing the surface area of the memory capacitor, the main disadvantages lies in its over-complicated manufacturing steps involved, which therefore greatly increases the production cost as well as production time.